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.- -- I - If- \-- THE MAXC MICROPROCESSOR MAXC 0.1 March 2, 1972 B u t 1 er Lampson Ed Fiala E d McCreight Chuck Thacker Xerox Palo A l t o Research Center 3180 P o r t e r Drive P a l o Alto, CA 94304 --, - , I f MICROPROCESSOR / Lampson, e t al. MAXC 8.1 / Page 2 Xerox P a l o Alto Research C e n t e r March 2, 1972 C 1.0 Overview 1.1 N o t a t i o n 20 C o n t r o l . 2.1 Interrupts 2.2 Flag Register 3.0 Ar it hme t ic/Lo g i c Sect i o n 3.1 R e g i s t e r Banks 3.2 P and Q R e g i s t e r s ; C y c l e and Mask 3.3 A r i t h m e t i c and Logic O p e r a t i o n s 3 . 4 Communication w i t h t h e Bus 4 . 0 Local Memories 4.1 Scratch Pad Memory 4.2 D i s p a t c h Memory 4.3 Map 44 . Instruction Memory 5 . 0 Memory I n t e r f a c e . 6.0 Maintenance I n t e r f a c e , 7 . 0 Disk C o n t r o l Appendix A Summary of M i c r o i n s t r u c t i o n Bits Appendix B Summary of Branch C o n d i t i o n s Appendix C Summary of P r i m a r y a n d Secondary F u n c t i o n s Appendix D Summary of Bus S o u r c e s and D e s t i n a t i o n s Appendix E Summary of F l a g R e g i s t e r B i t s Appen3ix F Summary o f System Maintenance I n t e r f a c e I n s t r u c t i o n s . ( N o t written yet) Appendix G More Than You R e a l l y Wanted t o Xnaw About D i s k Control Table 1.. I n s t r u c t i o n S e q u e n c i n g and S t a c k Actions Table 2. P Input S e l e c t i o n Table 3. Q Input Selection Table 4.. ALU F u n c t i o n s Table 5 0 . KSET-, KCSET-, and KSTAT Bus B i t s Fi